High-speed input/output (I/O) circuits require proper impedance matching between an off-chip circuit and on-chip circuitry to ensure efficient power transfer and signal integrity. In order to obtain good impedance matching between the off-chip circuit and the on-chip circuitry such as an on-chip I/O circuit, the impedance of the on-chip circuitry should match as closely as possible to the impedance of the transmission line between the on-chip circuitry and the off-chip circuit.
The parasitic capacitance in an on-chip circuit, however, may adversely affect the impedance matching between the off-chip circuit and the on-chip circuit (e.g., an on-chip I/O circuit). As an example, the parasitic capacitance in an on-chip I/O circuit may be contributed by an electrostatic discharge (ESD) protection circuit within the I/O circuit.
Generally, impedance matching techniques may include, among others, coupling an on-chip termination resistor to the affected I/O circuit, and including a T-coil circuit (either symmetrical or asymmetrical) in the on-chip circuitry. Conventional T-coil circuit structures, however, may not provide a good magnetic coupling factor and may be effective only at relatively low resonant frequencies.
It is within this context that the embodiments described herein arise.